FEC defined by very sparse parity check matrices

Low Density Parity Check Codes (LDPCs)

FEC Defined By Very Sparse Parity Check Matrices

LDPC is a powerful FEC option that is defined by very sparse parity check matrices. LDPC designs allow for parallel iterative decoder processing which can be implemented in a hardware-friendly fashion while maintaining excellent performance close to the Shannon limit. These cores use our proprietary, efficient, and scalable architectures for implementing LDPC encoders and decoders.

Available LDPC Products: 

FEC LDPC Products

LDPC Encoder and Decoder Cores:

  • DVB-S2 compliant LDPC + BCH concatenated
  • ECC-proprietary LDPC
  • Rate 7/8 LDPC
  • Ask about customized LDPC cores for your specific applications

Key LDPC Core Features:

  • Parallel iterative decoder processing
  • Viasat-proprietary, highly efficient algorithms
  • Excellent performance close to Shannon limit with minimal implementation loss
  • Scalable for throughput versus complexity trade-off
  • Fully synchronous single-clock design that can be clocked at very high speeds
  • On-the-fly configurable for ACM/VCM applications
  • Basic building blocks readily available in FPGA/ASIC libraries
  • Hardware proven

LDPC Codec Cores Formats:

  • Encrypted RTL
  • Synthesized netlist
  • Pre-compiled macro
  • Fully integrated FPGA bit file