Low Density Parity Check Codes (LDPCs)Low Density Parity Check Codes (LDPCs)
We offer a variety of proprietary and standard-compliant LDPC codec (encoder and decoder) cores for a diverse spectrum of satellite, mobile, and optical communication applications.
LDPC is a powerful FEC option that is defined by very sparse parity check matrices. LDPC designs allow for parallel iterative decoder processing which can be implemented in a hardware-friendly fashion while maintaining excellent performance close to the Shannon limit. These cores use our proprietary highly-efficient and scalable architectures for implementing LDPC encoders and decoders.
Available LDPC products
Choose from these LDPC encoder and decoder cores:
- DVB-S2 compliant LDPC + BCH concatenated
- ECC-proprietary LDPC
- Rate 7/8 LDPC
- Ask about customized LDPC cores for your specific applications
Key LDPC core features:
- Parallel iterative decoder processing
- ViaSat-proprietary, highly efficient algorithms
- Excellent performance close to Shannon limit with minimal implementation loss
- Scalable for throughput versus complexity trade-off
- Fully synchronous single-clock design that can be clocked at very high speeds
- On-the-fly configurable for ACM/VCM applications
- Basic building blocks readily available in FPGA/ASIC libraries
- Hardware proven
Based on your needs, we supply our LDPC codec cores in one of the following formats:
- Encrypted RTL
- Synthesized netlist
- Pre-compiled macro
- Fully integrated FPGA bit file